1. Technical Field
Embodiments of the invention relate to systems and methods for transmitting digital data.
2. Description of the Background
Digital devices in general, and computers in particular, have used buses in one form or another to exchange digital data. In some instances the bus has allowed diverse digital devices such as central processing units (“CPUs”), main memory cards, hard disks, input/output devices and other digital devices to share data through the use of a common bus. Today the bus is widely used as a convenient means of carrying digital data information through a set of parallel conductors, or other devices permitting digital communications such as optical fibers. In order for different digital devices to utilize the same bus, standards for the transmission and reception of digital data on that bus are often defined. These standards often include the use of an associated clock in order to prevent data collision and increase the overall throughput of the bus. For example, standards define the exchange of data for RAMBUS and synchronous dynamic random access memory (“SDRAM”) that enable the synchronous data transfer through a bus with the use of a clock. Such clocked buses sometimes have a separate clock line to allow a phase-locked loop (“PLL”) or a delay-locked loop (“DLL”) to sync up data transmission/reception circuitry with the actual data being exchanged. As such digital devices utilizing buses continue to increase in the speeds they operate at and communicate with, the buses have had to keep pace. This continued increase in bus throughput has put increasing importance on the accuracy of clock signals used to control such buses. Clock signals are generated and distributed to the devices connected to a given bus, but previously minor temporal differences (“skew”) between individual clock signals and each bit of data being carried on a bus can now significantly affect the overall performance of the bus at high-speeds.
Skew between clock signals and data signals can occur for many reasons. For example, the conductive lines used in many computer buses can suffer from different time delays and different transmission characteristics between such lines due to line mismatch, parasitic mismatch, device mismatch, impedance mismatch, etc. Often times individual data bits and clock bits have dedicated lines that display such differences in transmitting digital signals. Unfortunately, these differences become exacerbated as the underlying speed of the bus is increased and such differences in the time delays can create a limitation on the maximum bandwidth attainable for a high-speed bus.
Therefore, it would be desirable to provide a high-speed bus that overcomes or mitigates the problems described herein.
The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.